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Quadric

Quadric is a semiconductor IP company that makes the Chimera™ GPNPU (General-Purpose Neural Processing Unit) — licensable processor IP cores that run ML inference and complex C++ DSP code on a single, fully programmable, unified processor. SoC designers license Chimera RTL to build AI-capable chips without the complexity of pairing separate NPUs, DSPs, and CPUs.

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# Quadric

> Quadric is a semiconductor IP company that makes the Chimera™ GPNPU (General-Purpose Neural Processing Unit) — licensable processor IP cores that run ML inference and complex C++ DSP code on a single, fully programmable, unified processor. SoC designers license Chimera RTL to build AI-capable chips without the complexity of pairing separate NPUs, DSPs, and CPUs.

## What Is Quadric?

Quadric provides AI/ML processor IP for the chip design market. Their flagship product, the Chimera GPNPU, is a licensable processor IP core delivered as synthesizable RTL. SoC designers embed it into custom chips targeting inference applications in mobile, automotive, digital home, and network edge systems.

Quadric's Chimera IP scales from **1 TOPS** single-core (QC Nano) to **864 TOPS** multicore clusters (eight QC Ultra cores). All cores share a single ISA, a single software stack, and a single toolchain — code written for one Chimera core runs on any other.

Target applications include:
- ADAS and autonomous driving (camera, radar, lidar fusion)
- In-cabin monitoring and driver alertness
- Smart home and imaging subsystems
- Network edge compute
- Generative AI, LLMs, and transformer inference on device

## The Problem Quadric Solves

Modern SoC designs for AI applications traditionally require three separate IP blocks — a fixed-function NPU for ML graph inference, a DSP for signal processing, and a CPU for control code. This "multi-IP mess" creates serious problems:

1. **Multiple IP blocks** — Separate NPU, DSP, and CPU that must be integrated, debugged, and maintained independently, often from different vendors.
2. **Split toolchains and codestreams** — Each processor requires its own compiler and debugger; AI workloads must be artificially partitioned across cores.
3. **Fixed-function NPUs** — Hardware hardwired for last year's models. New ML operators require fallback to a slow CPU, causing up to a **1000× performance drop**. Custom operators simply cannot run at full speed.

The Chimera GPNPU solves this with a single unified core that is both **high-capacity** and **fully programmable**:

- **One execution pipeline** — Matrix, vector, and scalar (C++) operations run together, no partitioning required.
- **100% C++ programmable** — Every operator runs at full speed on the same parallel engine. New operators are added via C++ kernels and never blocked by silicon.
- **Single unified binary** — One codestream, one toolchain, one debug environment. ONNX graph code and C++ code merge into a single compiled binary.

This eliminates the need to switch between processors, reduces system power, and dramatically improves software developer productivity.

## Model Zoo

A "model zoo" is a collection of pre-ported AI models known to work on a specific hardware platform with acceptable accuracy. The term originates from the 2016–2017 era of open source model repositories (e.g. Hugging Face) and has since been adopted by every AI chip and NPU vendor to descr
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